The Anatomy of an SSD
SSD with two enclosed NAND flash memory chips installed. The controller chip is designed by PHISON.
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A. NAND Flash: The part where your data is stored, in blocks of non-volatile (does not require power to maintain data) memory.
B. DDR Memory: Small amount of volatile memory (requires power to maintain data) used to cache information for future access. Not available on all SSDs.
C. Controller: Acts as the main connector between the NAND flash and your computer. The controller also contains the firmware that helps manage your SSD.
- Single Level Cell (SLC)
- eMLC (enterprise Multi Level Cell)
- MLC (Multi Level Cell)
- TLC (Triple Level Cell)
| Flash Type | SLC (Single Level Cell) | eMLC (enterprise Multi Level Cell) | MLC (Multi Level Cell) | TLC (Triple Level Cell) |
| Read-Write Cycles | 90k-100k | 20k-30k | 8k-10k | 3k-5k |
| Cost | Most Expensive | Medium | Lower | Cheapest |
| Endurance | Highest | Medium | Lower | Lowest |
| Bits per Cell | 1 | 2 | 2 | 3 |
| Usage | Enterprise | Enterprise | Consumer/Gaming | Consumer |
| Write Speed | Highest | Medium | Lower | Lowest |
Reference :-
https://www.mydigitaldiscount.com/everything-you-need-to-know-about-slc-mlc-and-tlc-nand-flash.html
